The main aim of this project is to make it possible to run Vensim models in Simile. This involves writing a converter from Vensim syntax to Simile syntax. A subsidiary aim is develop the converter so that it can work in the reverse direction: i.e. that Simile models (at least, that subset of models which conform to Vensim's limited expressiveness) can be converted into Vensim syntax using the same converter run backwards.
This method for converting Vensim MDL files into Simile Prolog is based on 3 steps: